Multi-Layer PCB Design: 4-Layer Stack-Ups, Ground Planes, and When 2 Layers Isn't Enough

Our KiCad schematic-to-Gerber guide covers the general PCB design workflow on a standard 2-layer board, which is the right starting point for the vast majority of maker projects — an ESP32 breakout, a sensor carrier, a simple power board. But there's a point where a 2-layer board stops being a reasonable choice: dense BGA packages that need escape routing on multiple layers, high-speed signals that need controlled impedance, or a board crowded enough that you're fighting for trace space on every net. This guide covers what actually changes when you move to 4 layers, why it solves problems 2-layer routing can't, and how to set up a stack-up correctly in your CAD tool.

Why 2 Layers Runs Out of Room

On a 2-layer board, every trace you route on the top layer takes up space that competes with every other trace, and ground return current has to share the same routing layers as signals — there's no dedicated plane, so you rely on careful ground pours and stitching vias to keep return paths short. This works fine at the switching speeds and current levels of most Arduino/ESP32-class projects, but it degrades in three specific situations: fine-pitch BGA or QFN packages where pins are too dense to escape-route with only two layers, any signal fast enough to care about controlled impedance (USB, Ethernet, high-speed SPI to a display), and boards where thermal or EMI performance depends on an unbroken ground plane sitting directly under noisy components.

The Standard 4-Layer Stack-Up

The default stack-up nearly every fab offers, and the one you should default to unless you have a specific reason not to, is:

LayerAssignmentPurpose Top (L1)Signal + componentsPrimary routing and component placement Inner 1 (L2)Ground plane (GND)Continuous return path directly under top-layer signals Inner 2 (L3)Power plane (or mixed power/signal)Distributes supply rails with low impedance; splits allowed for multiple voltages Bottom (L4)Signal + componentsSecondary routing, often used for less critical nets

Placing a solid ground plane directly beneath the top signal layer is the single highest-value change a 4-layer stack-up gives you: every top-layer trace now has a tightly-coupled return path immediately below it, which controls impedance predictably, reduces EMI radiation, and shields other layers from top-layer switching noise. Keep the ground and power planes as unbroken as practically possible — every slot or split you cut into a plane for routing convenience creates a longer return path for whatever signal crosses it, which is a common, hard-to-diagnose source of noise on boards that "should" work fine on paper.

Setting Up the Stack-Up in KiCad

In the PCB Editor, open Board Setup → Physical Stackup and set the layer count to 4. KiCad's default 4-layer preset already assigns In1.Cu and In2.Cu as inner copper layers — rename them GND and PWR in the layer manager so intent is obvious to anyone (including future you) opening the file.
Set copper weight and dielectric thickness per your fab's standard offering (most fabs publish a default stack-up like 1.6mm total, 1oz outer/1oz inner copper) rather than customizing unless you have an impedance target that requires it — custom stack-ups cost more and add lead time.
Pour a ground plane on the GND inner layer covering the full board outline, and a power plane (or split power zones for multiple rails) on the PWR inner layer, then run Zone → Fill All Zones after routing to confirm no unintended gaps.
Add stitching vias connecting top and bottom ground copper to the internal ground plane every 5-10mm around the board perimeter and near any RF or high-speed sections — this keeps all ground references at the same potential and closes return paths for signals that cross layers.

Vias and Layer Transitions

A standard through-hole via connects all four layers whether a net needs it or not, which is fine for most maker-scale 4-layer boards and is what your fab will quote by default. Blind and buried vias (connecting only a subset of layers, e.g. top-to-inner) exist for higher-density boards but add significant cost and are rarely worth it below 6 layers — don't reach for them unless a specific BGA escape-routing problem demands it. When a signal must change routing layers, place the via as close to the pin as practical to minimize the length of trace on the "wrong" reference plane, and for any signal you care about impedance-wise, add a ground via next to the signal via so the return path has a continuous path through the layer transition too.

Controlled Impedance Basics

USB 2.0 differential pairs (90Ω), Ethernet (100Ω differential), and most high-speed serial links specify a target impedance that depends on trace width, copper thickness, and the dielectric height to the nearest reference plane — which is exactly why a 4-layer stack-up with a ground plane one layer below your signal layer makes controlled impedance practical in the first place. Use your fab's impedance calculator (JLCPCB, OSH Park, and others publish stack-up-specific calculators) rather than a generic formula, since dielectric constant and thickness vary by fab and material, and route differential pairs as matched-length, tightly-coupled parallel traces per your CAD tool's differential pair routing tool rather than as two independently routed single traces.

When to Actually Go 4-Layer

Not every project needs it, and the added cost (roughly 2-3x a comparable 2-layer board through JLCPCB or similar low-cost fabs, per our JLCPCB ordering guide) is real. Reach for 4 layers when you're routing a BGA or fine-pitch QFN with no room to escape-route on 2 layers, when a datasheet explicitly specifies controlled impedance for a signal you're routing, when EMI is a known problem (a board going near sensitive RF, or one that needs to pass emissions testing), or when a 2-layer version of the same design already has you fighting to fit traces. For everything else — most sensor boards, breakout boards, and simple power circuits — 2 layers remains the right, cheaper choice.

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